Public Lecture #3

"Cross-Layer Design for Enhancing the Resilience of In-Memory Computing to Device Variations"

Prof. Sharon HU (University of Notre Dame)

Abstract

In-memory computing (IMC) holds great potential for alleviating the data-transfer bottleneck in many data-intensive applications such as machine learning, bioinformatics, and secure information processing. For example, crossbar (XBAR) structures utilizing non-volatile memory (NVM) devices such as resistive RAM (ReRAM) and ferroelectric FETs (FeFETs) have been extensively studied for conducting in-memory matrix-vector multiplications, especially for accelerating various neural network (NN) models. However, the inherent variations in NVM devices can significantly impact the accuracy of in-memory computation, often necessitating costly solutions to mitigate this impact.

This talk presents our cross-layer design efforts aimed at addressing the impact of NVM device variations on IMC accuracy, using XBAR-based neural network accelerators as a proxy.  The talk first introduces models for quantifying the worst-case impact of device variations on NN accuracy, which is especially important for mission-critical applications. Then several device-circuit-algorithm codesign approaches to enhancing NN accelerator accuracy are discussed. Evaluation results, based on realistic device parameters, demonstrate the effectiveness of these approaches in enhancing the resilience of IMC accelerators to device variations.