Design Space Exploration of Deep Learning Architecture

"HW/SW Co-Exploration to Enable Automated Machine Learning System Design"

Prof. Weiwen JIANG (GMU)

Abstract

Since the "AI democratization" concept was proposed in 2017, researchers have devoted themselves to push forward its progress to enter the AI democratization era, where everyone in every field can enjoy the power of AI. In the early stage, a conventional design flow that separates the optimizations of AI model and hardware acceleration has demonstrated the possibility of integrating AI to different platforms, varying from edge to cloud; however, due to the software and hardware optimizations are highly coupled, such a separate optimization will lead to the inferior solutions. In 2019, we proposed the first co-design framework to bridge these two design spaces by taking FPGA as a vehicle and using Neural Architecture Search as the fundamental search engine. Then, we extend the co-design framework to support other hardware platforms, including Cloud GPU, Mobile GPU, Computing-in-Memory, and ASIC. Most recently, we apply the co-design philosophy to quantum computing and demonstrate the quantum advantages for neural networks for the first time. In this talk, we will present our co-design methodology, focusing on quantum computing. Our results have shown great potential for delivering the best neural networks and hardware accelerator designs to support AI democratization. The co-design frameworks for FPGA and ASICs obtained the Best Paper Nomination in DAC'19, CODES+ISSS'19, and ASP-DAC'20. 

References

1. Jiang, Weiwen, Xinyi Zhang, Edwin H-M. Sha, Lei Yang, Qingfeng Zhuge, Yiyu Shi, and Jingtong Hu. "Accuracy vs. efficiency: Achieving both through fpga-implementation aware neural architecture search." In Proceedings of the 56th Annual Design Automation Conference 2019, pp. 1-6. 2019.
2. Jiang, Weiwen, Lei Yang, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Shouzhen Gu, Sakyasingha Dasgupta, Yiyu Shi, and Jingtong Hu. "Hardware/software co-exploration of neural architectures." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, no. 12 (2020): 4805-4815.
3. Sheng, Yi, Junhuan Yang, Yawen Wu, Kevin Mao, Yiyu Shi, Jingtong Hu, Weiwen Jiang, and Lei Yang. "The Larger The Fairer? Small Neural Networks Can Achieve Fairness for Edge Devices." arXiv preprint arXiv:2202.11317 (2022). Accepted by DAC’22
4. Yang, Junhuan, Yi Sheng, Sizhe Zhang, Ruixuan Wang, Kenneth Foreman, Mikell Paige, Xun Jiao, Weiwen Jiang, and Lei Yang. "Automated Architecture Search for Brain-inspired Hyperdimensional Computing." arXiv preprint arXiv:2202.05827 (2022). Accepted by AutoML-Conf 2022

"Agile Arithmetic Optimization in AI Computing: From Architecture to Layout"

Prof. Yuzhe MA (HKUST GZ)

Abstract

The arithmetic elements are the most fundamental components in today's AI accelerators. Optimizing the arithmetic units is essential to achieve satisfactory performance, power, and area of AI accelerators. However, it is non-trivial to search in the enormous design space induced by massive possible architectures in the front end and complicated design flow in the back end. This talk will investigate several agile design methodologies to enable efficient and automatic arithmetic optimization. Firstly, we will introduce how to search for the desired arithmetic architecture in a giant design space using graph learning and active learning. Secondly, we will discuss how to achieve a good layout quality after the back-end flow through automatic design-flow tuning. Finally, we will discuss current challenges and possible directions for future research on arithmetic optimization.

"Exploring Design Solutions through AI-assisted Prediction and Parameter Tuning"

Prof. Zhiyao XIE (HKUST)

Abstract

Modern industrial chip design flows are immensely complex and consist of many design options and parameters, which lead to a huge overall circuit solution space. In this huge space, the impact of any design option on final chip quality cannot be accurately evaluated till late design stages. This makes explorations of solution space painfully time-consuming and heavily rely on human expertise. The ever-increasing design complexity in designs like AI accelerators further exaggerates the challenge. To improve the efficiency in chip quality optimization, we believe essential improvement on design predictability is necessary. In this talk, I will introduce our recent design automation methods for both early-stage design quality prediction and design flow parameter tuning. These methods are more focused on logic synthesis and layout stages. Based on customized machine learning (ML) techniques, various key design objectives including power, timing, routability can be evaluated in early chip design stages. Besides prediction, our design flow tuning method can efficiently explore the solution space and optimize the final chip quality without any human interference.