Workshop #2
Memory Driven Hardware Accelerators for Ultra Efficient Edge AI
"Architecting compute memories for ultra-efficient edge machine learning"
Dr. Giovanni ANSALON (École Polytechnique Fédérale de Lausanne (EPFL))
Abstract
The demise of scaling laws and the unabated increase in AI workloads is fostering disruptive approaches for next-generation computing architectures. Among those, compute memories (CMs) are especially attractive: they have the potential to reduce ever-more costly data movements, while leveraging the massive parallelism offered by the hierarchical organization of memory arrays. Nonetheless, the development of CM solutions is hampered by the paucity of exploration frameworks for investigating hardware/software co-designed solutions. In this talk, I illustrate two approaches that aim to address this challenge, based on open hardware and system simulation frameworks, respectively. The talk details the architecture of domain-specific CMs for AI using these strategies, each resulting in a>100X performance increase over traditional processor-centric execution. I will highlight differences in capabilities, target scenarios, and implementation philosophies.
Dr. Giovanni ANSALONI (EPFL)
"Computing accelerators codesign to optimize memory usage in edge AI systems"
Prof. Wei Zhan (The Hong Kong University of Science and Technology (HKUST))
Abstract
3D reconstruction and neural rendering are critical enablers for AR/VR, robotics, and digital twins. However, deploying these workloads on edge devices is fundamentally bottlenecked by their large memory footprint, irregular data access patterns, and high computational cost. This talk presents a line of research that addresses this memory efficiency challenge through software-hardware co-design.
We first show how exploiting the inherent data sparsity in neural rendering through hash-based compression and a dedicated accelerator can achieve over 21× memory reduction and up to 95× speedup over edge GPUs. We then move beyond manual optimization by employing reinforcement learning to automate hardware-aware quantization, discovering more compact and efficient model configurations without expert intervention. Building on these insights, we further extend the co-design philosophy to billion-parameter transformer-based 3D reconstruction, combining calibration-free low-bit quantization down to 4 bits with a reconfigurable multi-precision accelerator that alleviates on-chip memory pressure from long-sequence processing. Across these efforts, a consistent theme emerges: jointly optimizing algorithms and architectures with memory efficiency as a first-class design objective is essential for enabling real-time, high-quality 3D reconstruction on resource-constrained edge platforms.
Prof. Wei Zhang (HKUST)
"Neuromorphic memory devices for bio-inspired computing at the edge"
Prof. Xumeng Zhang (Fudan University)
Abstract
Inspired by biological neural systems, brain-inspired intelligence, centered on neuron-driven event-driven perception and spiking neural network (SNN)-based computing, offers a promising paradigm for achieving natural and highly sparse signal representation. Memristive devices with intrinsic neurodynamics further provide essential hardware support for physical computing. Focusing on the theme of “Neuron-Driven Brain-Inspired Perception and Computing,” this presentation systematically presents the implementation of memristive neurons and highlights recent progress in multimodal perception, probabilistic encoding, and high-order dynamic representation. It also demonstrates the advantages of long-short-term fused synapses in tasks such as temporal weighting and trajectory prediction. Moreover, a neuron-driven brain-inspired perception-computing system is developed to enable real-time robotic control via electromyographic (EMG) signals, validating the efficiency of the proposed neuron-driven architecture. The presentation concludes with a summary and an outlook on future directions
Prof. Xumeng Zhang (Fudan University)