AI-Assisted EDA

"Hardware/Software Co-Design of Deep Learning Accelerators"

Prof. Yiyu SHI (University of Notre Dame)

Abstract

The prevalence of deep neural networks today is supported by a variety of powerful hardware platforms including GPUs, FPGAs, and ASICs. A fundamental question lies in almost every implementation of deep neural networks: given a specific task, what is the optimal neural architecture and the tailor-made hardware in terms of accuracy and efficiency? Earlier approaches attempted to address this question through hardware-aware neural architecture search (NAS), where features of a fixed hardware design are taken into consideration when designing neural architectures. However, we believe that the best practice is through the simultaneous design of the neural architecture and the hardware to identify the best pairs that maximize both test accuracy and hardware efficiency. In this talk, we will present novel co-exploration frameworks for neural architecture and various hardware platforms including FPGA, NoC, ASIC and Computing-in-Memory, all of which are the first in the literature. We will demonstrate that our co-exploration concept greatly opens up the design freedom and pushes forward the Pareto frontier between hardware efficiency and test accuracy for better design tradeoffs.

Reference

1. Weiwen Jiang, Lei Yang, Edwin Sha, Qingfeng Zhuge, Shouzhen Gu, Sakyasingha Dasgupta, Yiyu Shi and Jingtong Hu, "Hardware/Software Co-Exploration of Neural Architectures," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (39)12, pp. 4805 - 4815, 2020 (2021

"Accelerating Sparse Neural Network Inference via Compression at Runtime"

Prof. Tsung-Yi HO (CUHK)

Abstract

Sparse deep neural network (DNN) has become an important technique for reducing the inference cost of large DNNs. However, computing large sparse DNNs is very challenging because inference iterations can incur highly irregular patterns and unbalanced loads. To address this challenge, the recent HPEC Graph Challenge seeks novel high-performance inference methods for large sparse DNNs. Despite the rapid progress over the past four years, solutions have largely focused on static model compression or sparse multiplication kernels, while ignoring dynamic data compression at inference time which can achieve significant yet untapped performance benefits. Consequently, in this talk, we present a new GPU algorithm to accelerate large sparse DNN inference via compression at runtime. Our algorithm leverages data clustering to transform intermediate results into a sparser representation that largely reduces computation over inference iterations. Evaluated on both HPEC Graph Challenge benchmarks and conventional DNNs (MNIST, CIFAR-10), SNICIT achieves 6 ∼ 444× and 1.36 ∼ 1.95× speed-ups over the previous champions, respectively.

"Machine Learning in EDA: Challenges and Solutions"

Prof. Zhiyao XIE (HKUST)

Abstract

As the integrated circuit (IC) complexity keeps increasing, the chip design cost is skyrocketing. Semiconductor companies are in increasingly greater demand for experienced man-power and stressed with unprecedented longer turnaround time. Therefore, there is a compelling need for design efficiency improvement through new design automation techniques. In this talk, I will present multiple efficient chip design and implementation techniques based on machine learning (ML) methods, whose major strength is to explore highly complex correlations based on prior data. These techniques cover various chip-design objectives, with slightly more focus on early-stage design power modeling. In addition, I will discuss the challenges we encountered during the development of ML techniques and potential solutions.